May 3, 2026

Allwinner H5 -- the aarch64 MMU, sources of information

The following document is from ARM and is probably the best general reference:

The following (chapter D8) in the ARM documentation gives the VMSA (virtual memory system architecture). It is written by zombies and there is probably no living being that understands it, but it gives the legal definition of the system

These articles are pretty helpful: I like the article by "Mike" for its style and honesty.

Registers

The TCR configures the MMU and without understanding it, nothing else will make sense.

the TLB

The Cortex-A53 in the H5 has a 10 entry level L1 and 512 entry L2 TLB per core. These are are various flavors of invalidate operations.
We only see one of the three that follow used by U-boot: 
# __asm_invalidate_tlb_all
   switch_el x9, 3f, 2f, 1f
3:  tlbi    alle3
    dsb sy
    isb
    b   0f
2:  tlbi    alle2
    dsb sy
    isb
    b   0f
1:  tlbi    vmalle1
    dsb sy
    isb

Have any comments? Questions? Drop me a line!

Tom's electronics pages / tom@mmto.org